MAX1162AEUB+T【PDF 4/18 页】IC ADC 16BIT 200KSPS 10-MSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录2008

1页 2页 3页 [4页]5页 6页 7页 8页

MAX1162

16-Bit, +5V, 200ksps ADC with 10A

Shutdown

______________________________________________________________________________________

quency band of interest. Minimize noise by presenting

a low impedance (at the frequencies contained in the

noise signal) at the inputs. This requires bypassing AIN

to AGND, or buffering the input with an amplifier that

has a small-signal bandwidth of several MHz, or prefer-

ably both. AIN has 4MHz (typ) of bandwidth.

Distortion

Avoid degrading dynamic performance by choosing an

amplifier with distortion much less than the MAX1162’s

total harmonic distortion (THD = -102dB at 1kHz) at fre-

quencies of interest. If the chosen amplifier has insuffi-

cient common-mode rejection, which results in degraded

THD performance, use the inverting configuration (posi-

tive input grounded) to eliminate errors from this source.

Low temperature-coefficient, gain-setting resistors reduce

linearity errors caused by resistance changes due to self-

heating. To reduce linearity errors due to finite amplifier

gain, use amplifier circuits with sufficient loop gain at the

frequencies of interest.

DC Accuracy

To improve DC accuracy, choose a buffer with an offset

much less than the MAX1162’s offset (1mV (max) for +5V

supply), or whose offset can be trimmed while maintain-

ing stability over the required temperature range.

Serial Interfaces

The MAX1162’s interface is fully compatible with SPI,

QSPI, and MICROWIRE standard serial interfaces.

If a serial interface is available, establish the CPU’s ser-

ial interface as master, so that the CPU generates the

serial clock for the MAX1162. Select a clock frequency

between 100kHz and 4.8MHz:

1) Use a general-purpose I/O line on the CPU to pull

CS low.

2) Activate SCLK for a minimum of 24 clock cycles.

The serial data stream of eight leading zeros fol-

lowed by the MSB of the conversion result begins at

the falling edge of CS. DOUT transitions on SCLK’s

falling edge and the output is available in MSB-first

CLK

CHANGE MUX INPUT HERE

CONVERSION

IN1

IN2

IN3

IN4

OUT

ACQUISITION

4-TO-1

MUX

AIN

MAX1162

TIMING NOT TO SCALE.

Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式